The number of functional blocks in semiconductor devices continues to increase significantly as the integration of functionality into a single semiconductor device continues. A functional block may be a sensor for temperature or voltage, a clock controlling circuitry like programmable clock dividers (PLL), scan configuration controllers, or entire Built-In Self-Test (BIST) engines for memory or logic testing. Accessing, controlling, observing, or in more general terms “operating”, a large number of these functional blocks presents a challenge to designers.
Traditionally, functional blocks are daisy-chained in a single, serial access network. This leads to numerous scan operations for shifting data bits into and out from these functional blocks. To reduce the access time, reconfigurable scan networks such as those conforming to IEEE 1687-2014 and IEEE 1149.1-2013 are employed to replace the traditional serial access networks. Based on certain programming operations of special elements of the access network, parts of a reconfigurable scan network can go in and out of the scan path. FIG. 2 illustrates an example of a reconfigurable scan network 200 conforming to IEEE 1687-2014 (IJTAG). In this IJTAG network 200, a SIB (Segment Insertion Bit) 223 switches between two different access paths between a TDI (Test Data In) port 215 and a TDO (Test Data Out) port 217, which both belong to a TAP (Test Access Port) 210. The shorter access path directly connects the SIB 223 to a SIB 221 while the longer access path connects the SIB 223 to the SIB 221 through two TDRs (Test Data Registers) 235 and 236. In a similar way, a ScanMux (multiplexer) 240 combines two scan segments of the access network 200 and can select either one based on control data received.
As FIG. 2 shows, programmable components of a reconfigurable scan network such as the SIBs 221-223 and the ScanMux 240 in the scan network 200 allow the dynamic configuration of the access network to bring a specific functional block into the scope of the access network. These programmable components can be programmed by shifting configuration data into the shift flip-flops of the control register in them and latching the shifted bits into the parallel latches. The functional blocks of the circuit are controlled by the TDRs 231-236. This dynamic access network configuration minimizes the number of shift operations needed for operating the desired functional block(s). Additional advantages of such reconfigurable scan networks are derived from the ability to configure the access network according to power and clock domains. For example, placing a SIB in front of a power domain allows the part of the access network outside of this power domain remains operational when the power domain is switched off. In a similar way, hierarchical design entities can be taken in and out of the scope of the access network, enabling the bypass of every functional object within the respective design hierarchy entity.
Due to the increasing size and complexity of the reconfigurable scan network, it becomes likely that the reconfigurable scan network contains one or several manufacturing defects. This can cause a variety of erroneous behavior. For example a SIB may no longer switch between the different network branches, or a certain TDR bit is stuck at 1. Manufacturing tests will detect such defective networks, e.g. by failing to access the desired functional objects. However, such manufacturing tests will only reveal that the access network is broken. In order to understand which objects of the access network are (potentially) defective and what their respective defective behavior might be, additional, specific tests and diagnosis are needed.